Signal-folding technique cuts neuromorphic chip power use by 90% while keeping accuracy

Context Neuromorphic chips mimic the brain’s wiring by performing compute‑in‑memory, where data stays where it is stored. Devices built from two‑dimensional molybdenum disulfide (MoS2) offer fine electrostatic control, making them attractive for low‑power AI at the edge. Historically, boosting weight precision in such arrays required higher voltages or calibration steps, which drained power and limited scalability.

Key Facts The team introduced an in‑hardware signal‑folding scheme that uses two complementary folds: input signal folding lowers the operating voltage, while weight conductance folding spreads device variations across more conductance levels to keep precision high. Both folds are programmed into a vertical one‑transistor‑one‑resistor (1T‑1R) MoS2 crossbar array, which holds the folded signals for vector‑matrix multiplication. The signals are encoded into two combinatorial folded signals, allowing the array to perform the core operation with far less energy. Compared with the unfolded approach, the folded method cuts the power needed for that core operation by up to 90% while delivering similar accuracy and without any post‑fabrication calibration.

What It Means A 90% reduction in multiplication energy translates directly into longer runtimes for edge AI devices such as smart sensors or mobile processors, potentially extending battery life from hours to days. The technique also removes the need for energy‑hungry calibration circuits, simplifying chip design and lowering manufacturing cost. Researchers will next test the folded arrays in larger networks, benchmark them against real‑world workloads like image recognition and speech processing, and explore integration with standard CMOS processes to see if the savings hold at scale.